User interface: A matter of memory

March 15, 2017 // By Marcel Kuba, Cypress Semiconductor
How high-speed memory interface technology enables users of DRAM devices to reduce pin count, save space and cut system cost.

There is a common theme in user-interface design across almost every market sector: the use of advanced 2D and 3D graphics in user interface designs is becoming steadily more prevalent and more sophisticated. This is one-way traffic: once users have gained a taste for digital graphics displays, touchscreen controls and other graphical features, they do not want to go back to an older interface style based on mechanical dials, gauges, buttons and switches.

In general, the more detailed, sharp, attractive and dynamic the graphics, the more users like the interface. This means that microcontroller-based embedded systems of many kinds either are facing now, or are likely to face in the near future, a requirement to deploy a graphics display control platform of some kind. This platform will often need to be scalable to cope with constantly escalating user demand for more, bigger and better graphics and display capabilities.

A crucial element in such a platform is the memory system: the rendering of graphics calls for a large amount of fast memory capacity. Today, this need is typically met by a combination of non-volatile Flash memory for storage of static graphics content, and external DRAM for storage of dynamic content. Internal video RAM (VRAM) inside the microcontroller might in some cases store the most highly dynamic graphics content.

But while such a memory architecture offers proven performance, the need for separate memory interfaces between the DRAM and the MCU, and between the Flash device and the MCU, results in a high pin count, a large board footprint and a complex and expensive PCB. This article shows that the use of a new memory bus technology supporting both Flash and DRAM can address this problem effectively, reducing pin count, board footprint and system cost.

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