Infotainment

Delta-Sigma converters for audio output in an infotainment FPGA

Field programmable gate arrays (FPGAs) present an efficient and inexpensive alternative when it comes to implementing complete embedded systems along with important peripheral functions. The reconfigurable logic circuitry of an FPGA offers tremendous flexibility. A lesser known feature is that the outputs of a digital FPGA also permit various analogue applications.

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Field programmable gate arrays (FPGAs) present an efficient and inexpensive alternative when it comes to implementing complete embedded systems along with important peripheral functions. The reconfigurable logic circuitry of an FPGA offers tremendous flexibility during the development phase and the product life cycle in addition to presenting a highly efficient solution for parallel applications. A lesser known feature is that the outputs of a digital FPGA – on account of its flexibility and performance – also permit various analogue applications, as illustrated in the following.

Next-generation infotainment systems call for a uniformly open, scalable, flexible and reliable architecture, which also offers an attractive price-performance ratio. The parameterisable infotainment system PARIS from Altera has already shown how the system costs of a head unit can be greatly reduced by means of integration. The flexible integration of analogue components into the FPGA simplifies the system design significantly and makes further cost savings possible. The use of FPGA technology in an infotainment system calls for high-quality analogue signal processing. FPGAs satisfy these requirements, e.g. in analogue audio playback, by implementing special digital-to-analogue converters (DAC) in programmable logic. In this regard, the question arises as to whether or not the analogue audio quality is influenced by noise and distortion at the FPGA pins and other side-effects. Ultimately, it is about using FPGA technology to achieve a high-quality analogue audio signal at reasonable expense.

Delta-Sigma conversion

What is known as Delta-Sigma conversion presents a particularly good solution for digital to analogue conversion in an FPGA. This approach has already been dealt with in other publications, although a more detailed analysis of important quality features is required, e.g. the signal to noise ratio (SNR) and total harmonic distortion (THD) as well as a comparison of the quality of Delta-Sigma conversion on which these are based with consumer audio electronics. 

Figure 1: Fundamentals of Delta-Sigma-DAC

Based on an oversampling ratio (OSR), a Delta-Sigma-DAC (Figure 1) converts audio samples into a high-frequency bit stream – similar to pulse-width modulation. This bit stream is referenced at an FPGA I/O pin and interpolated using an external analogue low-pass filter. The average-values-over-time resulting from this correspond to the digital sample values and represent the analogue output signal. This signal can be used directly for further amplification and playback, or, in our case, for measurement. The key advantage of Delta-Sigma-Conversion is noise shaping, which shifts noise components from low frequencies to higher frequencies and thus reduces noise in the low-frequency audio domain. This results in a very good SNR (see also in “Continuous Time Sigma-Delta A/D-Conversion”, by M. Ortmanns, Springer-Verlag, 2006). In theory, the SNR improves with increasing oversampling ratio due to the lower quantisation noise. Likewise, the SNR improves for higher-order Delta-Sigma-DAC. To obtain qualitative and quantitative results, we implemented various Delta-Sigma-DAC configurations for a fully functional audio playback system on an Altera Cyclone III FPGA (Figure 2).

Figure 2: Audio playback system test set-up

Implementation

The audio software executed in an Nios II Soft-Core processor sends digital audio data to the audio controller, which buffers and synchronises the audio samples. These are subsequently converted via Delta-Sigma-DAC to directly drive an FPGA I/O pin. The FPGA I/O pins are referenced at 2.5 V, the external RC low-pass filter is designed for a 20 kHz cut-off frequency. For various configurations, we have experimented with 1st and 2nd order of Delta-Sigma-DAC as well as various OSR (using Delta-Sigma-DAC and I/O pin clock speed from 10 MHz to 300 MHz) in addition to an optional upsampling module. The upsampling comprises an interpolating digital 1st order low-pass filter (IIR structure) and therefore increases the sampling rate prior to Delta-Sigma-DAC. The required FPGA resources per audio channel are 266 Altera Logic Cells (LC) with upsampling and 196 LC without upsampling.

Test results

A number of discrete sine input signals were used by way of an input signal for each configuration. An Agilent Network Analyzer was used in each case to measure the frequency spectrum and to calculate the SNR and THD on the basis of these. It should be mentioned at this juncture that all the configurations deliver promising audio quality. Figure 3 shows a representative spectrum for a 1 kHz sine input signal. The configuration consists of a 1st order Delta-Sigma-DAC with a 100 MHz clock speed and upsampling.

Figure 3: Test results: 1 kHz input signal, 1st order Delta-Sigma-DAC at 100 MHz with upsampling

In addition, we came across the following effects: A higher oversampling ratio reduces the quantisation noise, however, at the cost of THD (harmonic distortion denotes integer multiples of the input signal frequencies). Due to the high oversampling, long repeating patterns occur and the Delta-Sigma-DAC oscillates - a phenomenon typically referred to as 'limit cycles'. Consequently, the inherently instable 2nd order Delta-Sigma-DAC requires extra work in order to stabilise the control circuit. Upsampling as a form of pre-processing prior to Delta-Sigma-DAC produces significant improvements. One explanation for this is that the higher sampling rate reduces the oversampling and therefore also the effects of limit cycles. At the same time, the higher number of samples also means greater precision of the conversion, which in turn reduces the quantisation noise. Over all measured sine input signals, upsampling improves both the SNR and the THD by approx. 6dB on average.

By way of conclusion, we compared the Cyclone III audio playback system with consumer electronic devices – namely, a Realtek ALS268 audio chip according to Intel HD audio standard in addition to an iPod Nano 4. To this end, the same measurement set-up and the same 1 kHz sine input signal were used. Figure 4 illustrates that the SNR of the FPGA approach is comparable with consumer audio electronics, whilst the THD is slightly worse (primarily due to the effects of the limit cycles). Under the justified assumption that it is possible to counter limit cycles in the Delta-Sigma-DAC with the aid of additional techniques, the quality of the FPGA approach for audio output should be on a par with consumer electronic audio equipment. An additional option is dithering, which means adding a 'low dose' noise to the input of each Delta-Sigma-DAC quantiser. We expect this to overcome the limit cycle issue in Delta-Sigma-DAC and to result in a better THD.

Figure 4: Comparison with consumer audio electronics

Summary

The outstanding flexibility and performance of today's FPGA I/O pins make it possible to use a digital FPGA to obtain high-quality analogue audio output directly out of an FPGA. FPGA-based Delta-Sigma-DACs can be simple and compact – the audio playback results are comparable with consumer electronic audio solutions used for infotainment systems. Future analyses will examine higher-order Delta-Sigma-DAC, in expectation of even better SNR and lower distortion by limit cycles. Since higher orders of Delta-Sigma-DAC are inherently instable, coefficient tuning for stable behaviour is mandatory. The implementation of dithering will allow the THD to be further reduced.

Appendix:

Nios II Embedded Processor

Nios II is a soft processor that can be instantiated on an Altera FPGA device. The processor and its associated memory and peripheral components are easily instantiated by using Altera's SOPC

Builder in conjunction with the Quartus II software. The Nios II processor can be used with a variety of other components to form a complete system. These components include a number of standard peripherals, but it is also possible to define custom peripherals.

The Nios II processor has a number of features that can be configured by the user to meet the demands of a desired system. The processor can be implemented in three different configurations:

• Nios II/f is a "fast" version designed for superior performance. It has the widest scope of configuration options that can be used to optimize the processor for performance.

• Nios II/s is a "standard" version that requires less ressources in an FPGA device as a trade-off for reduced performance.

• Nios II/e is an "economy" version which requires the least amount of FPGA resources, but also has a limited set of user-configurable features.

Cyclone III and Cyclone IV FPGAs

The features and architecture of the Cyclone III FPGAs provide the ideal solution for high-volume, low-power, cost-sensitive applications. With 200K logic elements (LEs) and 8-Mbits of memory for less than 1/4 watt of static power consumption, this family sets the power standard.  Cyclone III LS FPGAs are the first to offer a suite of security features at the silicon, software, and intellectual property (IP) level on a low power, high functionality FPGA. This suite of security features protects your IP from tampering, reverse engineering, and cloning. Additionally, these devices enable you to introduce redundancy in a single chip using design separation, which reduces the size, weight, and power of your applications.

The new Cyclone IV FPGA family offers two variants. Cyclone IV GX devices have up to 150K logic elements, up to 6.5-Mbits of RAM, up to 360 multipliers, and up to eight integrated 3.125-Gbps transceivers supporting mainstream protocols including Gigabit Ethernet (GbE), SDI, CPRI, V-by-One and Cyclone IV GX has hard IP for PCI Express (PCIe).  Cyclone IV E devices deliver an unprecedented combination of low cost and high functionality, and lower power by up to 25 percent compared to previous generation Cyclone products for power-sensitive applications such as handheld software-defined radio. 

Power

Battery

Automotive

Continental

Hammerschmidt

Powertrain

Ipetronik

GPS

E-car

Autosar

Fraunhofer

Bosch

NXP

Freescale

Infineon

Power MOSFET

Daimler

HEV

Infotainment

Neutrino

Ethernet

Linear Technology

BMW

FlexRay

Audi

National Semiconductor

QNX

China

RTOS

International Rectifier