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Freescale adds single-chip instrument cluster SoC to S12 MagniV family

March 21, 2012 | Christoph Hammerschmidt | 222902138
Freescale adds single-chip instrument cluster SoC to S12 MagniV family Freescale Semiconductor has introduced adding a device family designed primarily for the mainstream automotive instrument cluster market to its S12 MagniV mixed-signal microcontroller (MCU) portfolio. The new S12 MagniV S12ZVH enables developers to create a comprehensive instrument cluster solution with a single chip, significantly reducing time to market and the overall bill of materials.
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The S12ZVH 16-bit mixed-signal MCU family is based on Freescale's LL18UHV technology, which enables extensive analog integration on the MCU so automotive developers can connect high-voltage signals and power supplies directly to the MCU, helping save board space and reduce system complexity. By designing with the S12ZVH, developers also can minimize sourcing from multiple suppliers and improve overall system reliability. The company claims to be the first one to market with a single-chip solution for automotive instrument clusters. The device aims at entry-level cluster applications in which cost and board space are key drivers.

The S12ZVH is the first family in Freescale's S12 MagniV portfolio designed specifically for instrument clusters. The mixed-signal MCUs are targeted at instrument cluster applications requiring controller area network (CAN) connectivity, stepper motor gauges and segment LCD or dot-matrix displays.

Customers can benefit from the integration provided by the S12ZVH MCU platform, including familiar S12 MCU family features such as low power consumption and smart peripherals as well as features such as a CAN physical interface, a 5V regulator system to supply the MCU, a real-time clock and sound generator. Features unique to the S12ZVH family include 8K of ECC RAM and stepper stall detection capability.

The S12ZVH features an enhanced S12Z core that provides significant design benefits compared to prior versions. The addressing space is now linear (no memory paging required), simplifying software development and allowing it to easily port across applications. The efficiency of this new core allows code density improvement up to 40 percent, as well as faster execution than earlier 16-bit architectures.

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