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Safety & Security

Technical considerations and protection mechanism for ESD events in a mixed signal SoC

July 26, 2012 | Gurinder Singh Baghria, Naveen Kumar, Rishi Bhooshan,Sachin Kalra, Freescale | 222902396
Technical considerations and protection mechanism for ESD events in a mixed signal SoC In today's world, there is an ever increasing demand of speed, performance and features in a SOC and to cater for these needs, the industry is moving towards smaller device sizes. Although the decrease in device size does provide higher speed and performance, there are issues related to power and Electro-Static Discharge (ESD), which need to be addressed. The desire to add more features often results in sacrificing some of the on chip ESD protection. This trade off is a great risk for ESD. Thinner gate oxides, complex SOC chips with multiple power supplies and mixed-signal blocks, larger chip capacitances and faster circuit operation all contribute to increased ESD sensitivity of advanced semiconductor products.
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REQUIREMENTS OF ESD PROTECTION MECHANISM AT SOC

The sole aim of ESD protection strategy is to divert the ESD current spike away from sensitive circuitry and protect the system from permanent damage.


Figure 1: System Level Network Presentation

An ESD protection mechanism must fulfill the below requirements:

  1. It must provide dual polarity protection, i.e., should provide ESD protection in case of both positive and negative spikes.
  2. The ESD protection device must be able to handle high current transients.
  3. The ESD protection path must have very low resistance in case of ESD currents. Typical resistance value is 1 ohm.
  4. The ESD protection device clamps the voltage of sensitive circuits below safe functional voltage level.

The typical ESD protection methods used in SOCs are:

Distributed rail based clamp network; and

Snapback clamp protection devices.

Snapback Protection Method: The conventional snapback clamp protection method depends on the theory of avalanching junctions to trigger parasitic LNPN (lateral NPN) or Silicon Controlled Resistor (SCR). Most popular protection devices in snapback method are MOSFET and SCR. Under ESD conditions, these devices operate in breakdown region. The most important features of snapback based protection are as follows:

  • It can be made robust by optimization.
  • Being generally immune to false triggering, it can be used for fail safe applications.

On the other hand,

  • It is very much process dependent and difficult to simulate.
  • A ballast resistance is required to protect the NMOS output buffer.
  • The protection clamp may occupy large layout area and may add significant capacitance to IO pad.

The typical snapback I-V characteristics of protection device (Grounded gate NMOS) are shown in figure 2(b). With the increase in drain voltage, many electron-hole pairs are generated by impact ionization and the drain substrate junction of parasitic LNPN shown in figure 2(a) becomes more reverse biased and eventually goes into avalanche breakdown. Electrons that occur due to impact ionization flow to the drain and holes flow to the substrate so a potential start rises across the base of transistor and when this potential reaches 0.7V, the transistor gets forward biased and turns on. At this point, the drain voltage is marked as Vt1 and is called first breakdown voltage. The drain voltage is reduced to a level marked as VSB, (holding voltage) and from this point on, increase in the drain voltage increases the current until finally the device goes through thermal breakdown. This second breakdown voltage is marked as Vt2.

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