Formal-methods checking contributes to FPGA use in hi-rel designs

March 25, 2015 // By Graham Prophet
Microsemi and OneSpin Solutions (Munich and San Jose, California) are targeting high-reliability design verification with a formal-based FPGA equivalency checking solution; OneSpin’s 360 EC-FPGA is used to verify Microsemi FPGA designs, including SmartFusion2 SoC FPGAs and IGLOO2 FPGAs, for safety-critical applications.

OneSpin 360 Equivalence Checking (EC)-FPGA verification software now fully supports Microsemi’s Libero System-on-Chip (SoC) design flow. Equivalency checking, Microsemi notes, has become a critical component in the verification of high-reliability designs such as safety critical components, ensuring that no issues are introduced during the design refinement process. OneSpin’s EC-FPGA product augments Microsemi’s Libero design flow to ensure the functional consistency of high-reliability designs throughout design refinement, reducing the risk of an end-product fault.

“OneSpin Solutions has created innovative formal-based design verification and equivalence checking solutions that are being used to fully vet some of the most safety critical designs in production today,” said Bruce Weyer, vice president and business unit manager at Microsemi. “We believe that by including equivalence checking as part of the design flow, we will better meet our customers’ stringent requirements for high-reliability designs.”

For its SmartFusion2 and IGLOO2 FPGAs in 2013, Microsemi’s Libero SoC design software now has over 44,000 licenses granted year to date. Microsemi says its FPGAs are seeing mainstream applications for communication, industrial, aerospace and defence markets. By using OneSpin’s equivalence checker with Microsemi’s design flow, designers can gain assurance that when they implement the most aggressive design flow optimisations to improve FPGA device power consumption, performance and area utilisation, they do not introduce functional errors. The tool verifies functional equivalence between the register transfer level (RTL) code and the netlist prior to FPGA download, thus reducing prototype verification requirements and ensuring that no design flow bugs appear in the final device.

OneSpin says its 360 EC-FPGA eliminates design flow-generated errors in FPGAs, supporting complex sequential optimisations with a solution that accelerates schedules, reduces risk and increases product quality. The tool includes support for Verilog, SystemVerilog, VHDL, EDIF and mixed languages, and runs on the Linux and Solaris platforms. It also supports Microsemi’s SmartFusion2 SoC FPGAs, IGLOO2 and IGLOO FPGAs, ProASIC3 and Fusion FPGA devices.

OneSpin Solutions;