HILLSBORO, OR Sept. 24, 2013 Lattice Semiconductor has introduced a new ultra-low density FPGA family. The MachXO3 boasts with very small dimensions, very low power consumption and also very low cost per I/O. The programmable platform aims at expanding system capabilities and bridging emerging connectivity interfaces using both parallel and serial I/O. By matching small-footprint packaging with on-chip resources, the MachXO3 family simplifies the implementation of emerging connectivity interfaces such as MIPI, PCIe, GbE, and much more.
The ultra-low density MachXO3 family gives customers a single programmable bridge that lets them build differentiated systems using the latest components and interface standards. With advanced package technology solutions that eliminate bond wires to enable lowest-cost and increased I/O density in a small footprint, the MachXO3 family can be used across market segments, including consumer, communications, compute, storage, industrial and automotive.
Leveraging a low power architecture built on 40nm process technology to deliver lower cost with increased performance for power sensitive applications, the MachXO3 family delivers a new set of capabilities that enable system engineers to do even more in a smaller footprint.
The 640-to-22K logic-cell family makes use of the latest in package technology to not only deliver tiny 2.5x2.5mm wafer-level chip-scale packaging, but also 540 I/O count devices, as well as devices with 3.125Gbps SERDES capabilities to cover the full spectrum of bridging and interface requirements in consumer, industrial, communications, automotive, and compute markets.
For more information visit www.latticesemi.com/MachXO3.