Low pin-count HyperRAM memory now sampling

July 07, 2016 // By Julien Happich
Cypress Semiconductor is now sampling a new high-speed, self-refresh Dynamic RAM (DRAM) based on the company's low-pin-count HyperBus interface.

The 64Mb HyperRAM serves as an expanded scratchpad memory for rendering of high-resolution graphics or calculations of data-intensive firmware algorithms in a wide array of automotive, industrial and consumer applications. The devices operate with a read/write bandwidth of up to 333 MBps and are available in 3V and 1.8V supply voltage ranges.
When paired with a Cypress HyperFlash NOR Flash memory, HyperRAM enables a simple and cost-effective solution for embedded systems where both the flash and RAM reside on the same 12-pin HyperBus. Traditional systems with an SDRAM and Dual-Quad SPI solution require upwards of 41 pins on two buses for data transactions. The HyperRAM and HyperFlash solution reduces pin count by at least 28 pins, decreasing design complexity and lowering PCB cost.

The devices will be available in a 24-ball, 6-mm by 8-mm ball grid array (BGA) package.
To accelerate product design cycles, Cypress offers customers and partners a HyperBus Master Interface Controller IP Package that helps designers add support for HyperBus to their FPGA, ASIC or ASSP host controller platform. The Controller IP supports both HyperRAM, as well as HyperFlash products, and is free of charge and royalty-free.

Visit Cypress at www.cypress.com/hyperflash