Processor IP targets safety-critical applications

October 22, 2013 // By Christoph Hammerschmidt
For safety-compliant sensor applications in automotive environments, Synopsys has developed the DesignWare ARC EM SEP (Safety Enhancement Package) Processor core. Based on the highly efficient ARC EM4 core, this 32-bit processor IP addresses companies that intend to design complex automotive SoCs with adequate computing power.

The new processor core delivers performance up to 300 MHz at a power consumption of just 16 mW/MHz on typical 65nm low power silicon processes, with integrated hardware safety features that enable ASIL D compliance in support of the ISO 26262 standard. In addition, the DesignWare ARC MetaWare Compiler helps software developers accelerate the development of ISO 26262-compliant code and is undergoing ASIL D readiness certification by independent safety certification company SGS-TÜV Saar. The combination of a safety-enhanced processor and compiler makes the ARC EM SEP core ideally suited for system-on-chips (SoCs) designed for embedded automotive applications such as movement and acceleration sensors, advanced driver assistance systems and electric power steering.

The ARC EM SEP core is configurable in a wide range to meet the specific performance, power and area requirements of each target application. Giving designers the ability to define custom instructions facilitates the integration of proprietary hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required critical requirements in embedded automotive designs. The EM SEP processor integrates hardware safety features including ECC for single-bit error correction and double-bit error detection, and parity protection for single-bit error detection on closely coupled memories.

To minimise system-level latencies and silicon area, SoC peripherals can be directly mapped to the CPU to enable single cycle access. Native ARM AMBA, AHB, AHB-Lite and BVCI standard interfaces are configurable for 32-bit or 64-bit transactions to optimize system throughput. Support for ARC EM SEP in Synopsys' Virtualizer virtual prototyping environment allows for seamless integration with tools such as Mathworks’ Simulink, Vector’s CANoe and Synopsys’ Saber to enable virtual hardware-in-the-loop (HIL) simulation and fault testing.

The DesignWare ARC MetaWare Compiler and accompanying safety documentation help developers of safety critical systems fulfill the requirements of the ISO 26262 standard. The IP safety collateral, including a safety manual and safety guide, makes it easier for automotive designers to prepare their documentation for