The two companies are co-developing the next (5th) generation of Mobileye’s SoC, with a view to equipping Fully Autonomous Driving (FAD) vehicles starting in 2020. To meet power consumption and performance targets, the EyeQ5 will be designed in advanced 10 nm or below FinFET technology node and will feature eight multithreaded CPU cores coupled with eighteen cores of Mobileye's next-generation vision processors. Taken together, these enhancements will increase performance 8x times over the current 4th generation EyeQ4. The EyeQ5 will process more than 12 Tera operations per second, while keeping power consumption below 5W, to maintain passive cooling. Engineering samples of EyeQ5 are expected to be available by first half of 2018.
Building on its experience in automotive-grade designs, ST will support state-of-the-art physical implementation, specific memory and high-speed interfaces, and system-in-package design to ensure the EyeQ5 meets the full qualification process aligned with the highest automotive standards. ST will also contribute to the overall safety- and security-related architecture of the product.
“EyeQ5 is designed to serve as the central processor for future fully-autonomous driving for both the sheer computing density, which can handle around 20 high-resolution sensors and for increased functional safety,” said Prof. Amnon Shashua, cofounder, CTO and Chairman of Mobileye. "The EyeQ5 continues the legacy Mobileye began in 2004 with EyeQ1, in which we leveraged our deep understanding of computer vision processing to develop highly optimized architectures to support extremely intensive computations at power levels below 5W to allow passive cooling in an automotive environment.”
EyeQ5’s proprietary accelerator cores are optimized for a wide variety of computer-vision, signal-processing, and machine-learning tasks, including deep neural networks. EyeQ5 features heterogeneous, fully programmable accelerators, with each of the four accelerator types in the chip optimized for its own family of algorithms. This diversity of accelerator architectures enables applications to save both computational time and energy by using the most suitable core for every task. This optimized assignment