Synopsys IP speeds automotive SoC development

June 08, 2015 // By Christoph Hammerschmidt
In a semiconductor market environment in which the automotive section is hitting the gas pedal harder than any other, EDA tools company Synopsys is rounding off its offerings with a set of IP dedicated to this promising market. The enhancements of its DesignWare IP portfolio are even taking safety aspects into account – to a certain level.

The automotive market stands out amidst other application segments in that it has particular high requirements with regards to high integration as well as specific safety and reliability. From the engineering perspective, the integration and performance requirements translate into designs that increasingly make use of Systems-on-chip (SoCs) with multiple heterogeneous microprocessors along with applications logic, memory and interfaces in a single package. Synopsys supports this design trend in that it extends its DesignWare IP portfolio with a range of IP blocks that cast the most promising and future-oriented functions into silicon by means of RTL code or hard IP.

Safety-critical IP for automotive applications: Synopsys widens its offerings that help design engineers to speed their ADAS designs.

The offering includes Ethernet Audio Video Bridging (AVB), Low-power DDR4 memory, non-volatile memories, data converters and other functional units, all powered by Synopsys’ ARC microprocessor architecture. In addition, the offering includes a range of interface IP mostly used in the infotainment domain and Advanced Driver Assistance System (ADAS) applications like HDMI, PCI Express and USB. Most of these building blocks are pre-certified according to the safety standard ISO 26262, ASIL level B. While the B level is only the third-highest of four levels and thus does not inherently include the most safety-critical applications like power steering or everything around semi- or full automated driving, this does not rule out that the IP can be used in such systems, explained Jai Durgam, Synopsys Group Director of Field Applications Engineering, in an interview with EE Times Europe. In such cases however the design needs to be certified individually.

In any case, already the IP in question is delivered with safety packages that include failure mode effects and diagnostic analysis reports as well as safety plans and manuals, giving designers the documentation required to complete their own certification process. In addition, the development process for the Synopsys IP also supports the TS 16949 standard documentation requirements.